1. Field of the Invention
Example, non-limiting embodiments of the present invention relate generally to a lead frame for a semiconductor package and, more particularly, to a lead frame on which a tape may be provided.
2. Description of the Related Art
It may be desirable to provide electronic products that are miniaturized and light weight. Such electronic products may incorporate semiconductor packages arranged in a high density layout. Accordingly, it may be desirable to provide semiconductor packages with components that that are miniaturized and light weight.
A semiconductor chip (which may be a component of a semiconductor package) may have a plurality of chip pads. The chip pads may be provided at fine pitch. The semiconductor chip may be mounted on a lead frame having leads that may be connected to the chip pads of the semiconductor chip. Accordingly, the leads may be provided at a fine pitch. The pitch (or spacing between corresponding points) of the leads may decrease (or become finer) as the number of leads increases.
A fine lead pitch may reduce intervals between leads. In some instances, an electrical short may occur due to a contact between leads. A tape may be provided on the leads in an effort to maintain the desired interval between adjacent leads. The tape may promote a stable bonding process (e.g., a wire bonding process) in which the leads may be electrically connected to the chip pads. The tape may also reduced likelihood of electrical shorts. The tape may be formed of insulating materials.
A conventional lead frame 10 having a tape 14 is depicted in FIGS. 1 through 3. The lead frame 10 may be fabricated from a Cu material. The lead frame may be implemented in a quad flat pack (QFP), for example. In general QFPs may have a rectangular (or square) shape, with leads provided on all four sides. The lead frame 10 may include a frame body 19, tie bars 11, a die pad 12, and a plurality of leads 17. The frame body 19 may have a square shape. The tie bars 11 may extend toward the die pad. The die pad 12 may have a square shape and be located at the center of the frame body 19. The die pad 12 may provide a location upon which a semiconductor chip may be mounted. The die pad 12 may be connected to the tie bars 11. The leads 17 may extend toward the die pad so that ends of the leads 17 may be arranged along the periphery of the die pad 12.
A tape 14 may be arranged on the frame body 19. The tape 14 may fix the tie bars 11 and leads 17 to the frame body. The tape 14 may include a film 14a fabricated from an insulating material and an insulating adhesive layer 14b provided on a surface of the film 14a. 
A deformation of the lead 17 may result in a contact between adjacent leads 17, causing an electrical short. The tape 14 may maintain the position of the leads 17 with its adhesive strength, thereby reducing the likelihood of leads 17 becoming in contact with each other.
The leads 17 may include inner leads 13 extending toward the die pad 12. The leads 17 may also include outer leads 16 extending toward the frame body 19. Each inner leads 13 and a corresponding outer leads 16 may be of unitary, one-piece construction. A dam bar 15 may be provided on the frame body 19 and extend across the leads 17.
As shown in FIG. 2, each inner lead 13 may include a bonding portion 21 where a semiconductor chip may be electrically connected, and an attaching portion 22 where the tape may be provided. The bonding portion 21 and the attaching portion 22 may have the same width. An Ag plating layer 23 may be provided on the bonding portion 21.
Although conventional lead frames 10 are generally thought to provide acceptable performance, they are not without shortcomings. For example, a potential difference may occur between adjacent inner leads 13 of the lead frame 10. In this case, as shown in FIGS. 4 and 5, a dendrite 24 may be formed due to the movement of Cu ions across the tape 14. In some cases, the dendrite 24 may extend between adjacent leads and cause an electrical short between the leads 17.
For example, during a reliability test (such as a high temperature operating life test, for example) of a resultant semiconductor package after a sealing process using a molding compound 18, a potential difference may occur between adjacent inner leads 13. The electric field caused by the electrical potential difference may ionize Cu atoms contained in the inner leads 13. The ionization of Cu atoms may be generated in an attaching portion 22a of an anode (+) inner lead of the inner leads 13. Generally, the Cu ions of the anode (+) attaching portion 22a may diffuse and migrate along the tape 14 toward a cathode (−) attaching portion 22b of an adjacent inner lead 13 to create the dendrite 24. The dendrite 24 may grow to such an extent that it may come into contact with the attaching portion 22b, resulting in an electrical short between adjacent inner leads 13. FIG. 5 shows an electrical short that may occur between adjacent inner leads 13 due to a dendrite grown via the migration of Cu ions across the tape attaching portion.